/*
 * Copyright (c) Huawei Technologies Co., Ltd. 2012-2020.
 * Description: The C union definition file for the module GE_8_11
 * Author: yanbo
 * Create: 2012-12-25
 */
#ifndef GMAC_GE_REG_H
#define GMAC_GE_REG_H

/* Define the union duplex_type */
/* full-duplex half duplex mode register */
/* 0x8 */
union duplex_type {
	/* Define the struct bits */
	struct {
		/* [ 31..1 ] cannot be configured. */
		unsigned int reserved_0 : 31;
		/* [ 0 ]: 1: full-duplex; 0: half-duplex. */
		unsigned int duplex_sel : 1;
	} bits;

	/* Define an unsigned member */
	unsigned int    u32;
};

/* Define the union FD_FC_TYPE_U */
/* FD_FC_TYPE type domain register for flow control frames. */
/* 0xC */
typedef union tagfdfctype {
	/* Define the struct bits */
	struct {
		/* [ 31..16 ] cannot be configured. */
		unsigned int reserved_1 : 16;
		/* [ 15..0 ] full-duplex sends pause frames.  TYPE domain */
		unsigned int fd_fc_type : 16;
	} bits;

	/* Define an unsigned member */
	unsigned int    u32;
} fd_fc_type_u;

/* Define the union FC_TX_TIMER_U */
/* FC_TX_TIMER is the flow control time parameter register. */
/* 0x1C */
typedef union tagfctxtimer {
	/* Define the struct bits */
	struct {
		/* [ 31..16 ] cannot be configured. */
		unsigned int reserved_2 : 16;
		/* [ 15..0 ] time parameters sent flow control frames. The unit is 512bit. */
		unsigned int fc_tx_timer : 16;
	} bits;

	/* Define an unsigned member */
	unsigned int    u32;
} fc_tx_timer_u;

/* Define the union FD_FC_ADDR_HIGH_U */
/* FD_FC_ADDR_HIGH is destination address register 2 flow control frames. */
/* 0x24 */
typedef union tagfdfcaddrhigh {
	/* Define the struct bits */
	struct {
		/* [ 31..16 ] cannot be configured. */
		unsigned int reserved_4 : 16;
		/* [ 15..0 ] Flow control DA address high 16bit. */
		unsigned int fd_fc_addr_high : 16;
	} bits;

	/* Define an unsigned member */
	unsigned int    u32;
} fd_fc_addr_high_u;

/* Define the union IPG_TX_TIMER_U */
/* IPG_TX_TIMER is Transmit IPG register. */
/* 0x30 */
typedef union tagipgtxtimer {
	/* Define the struct bits */
	struct {
		/* [ 31..8 ] cannot be configured. */
		unsigned int reserved_5 : 24;
		/* Transmit IPG [ 7..0 ]. The unit is byte. */
		unsigned int ipg_tx_timer : 8;
	} bits;

	/* Define an unsigned member */
	unsigned int    u32;
} ipg_tx_timer_u;

/* Define the union PAUSE_THR_U */
/* PAUSE_THR IPG register for sending flow control frames. */
/* 0x38 */
typedef union tagpausethr {
	/* Define the struct bits */
	struct {
		/* [ 31..16 ] cannot be configured. */
		unsigned int reserved_7 : 16;
		/* [ 15..0 ] interval for sending flow control frames. */
		unsigned int pause_thr : 16;
	} bits;

	/* Define an unsigned member */
	unsigned int    u32;
} pause_thr_u;

/* Define union max_frm_size */
/* MAX_FRM_SIZE is max frame length register. */
/* 0x3C */
union max_frm_size {
	/* Define the struct bits */
	struct {
		/* [ 31..16 ] cannot be configured. */
		unsigned int reserved_9 : 16;
		/* [15..0] MAC frame max length allowed. */
		unsigned int max_frm_size : 16;
	} bits;

	/* Define an unsigned member */
	unsigned int    u32;
};

/* Define the union port_mode */
/* PORT_MODE is a port status register. */
/* 0x40 */
union port_mode {
	/* Define the struct bits */
	struct {
		/* [ 31..8 ] cannot be configured. */
		unsigned int reserved_10 : 24;
		/* [ 7 ] RX clock loss protection function is shielded: 0: not masked */
		unsigned int dbg_clk_los_msk : 1;
		/* [6] FIFO is empty and full GMAC automatically reset enable. 0: disabled 1: enabled */
		unsigned int fifo_err_auto_rst : 1;
		/* [5] MII transmit direction collection channel associated clock
		 * edge select 0: The rising edge 1: collection falling edge
		 */
		unsigned int mii_tx_edge_sel : 1;
		/* [4] RGMII mode transmit direction associated clock: 0: normal mode: aligned with the data. */
		unsigned int rgmii_1000m_delay : 1;
		/* [ 3..0 ] The MAC port working mode. */
		unsigned int port_mode : 4;
	} bits;

	/* Define an unsigned member */
	unsigned int    u32;
};

/* Define the union PORT_EN_U */
/* PORT_EN is the channel enable register. */
/* 0x44 */
typedef union tagporten {
	/* Define the struct bits */
	struct {
		/* [ 31..3 ] cannot be configured. */
		unsigned int reserved_11 : 29;
		/* [ 2 ] The channel enable. */
		unsigned int tx_en : 1;
		/* RX channel enable [ 1 ]. */
		unsigned int rx_en : 1;
		/* [ 0 ] cannot be configured. */
		unsigned int reserved_12 : 1;
	} bits;

	/* Define an unsigned member */
	unsigned int    u32;
} port_en_u;

/* Define the union PAUSE_EN_U */
/* PAUSE_EN is flow control enable register. */
/* 0x48 */
typedef union tagpauseen {
	/* Define the struct bits */
	struct {
		/* [ 31..3 ] cannot be configured. */
		unsigned int reserved_13 : 29;
		/* [ 2 ] enable JAM frames sent in half-duplex mode. */
		unsigned int tx_hdfc : 1;
		/* [ 1 ] in full duplex mode enable.  sent flow control frames */
		unsigned int tx_fdfc : 1;
		/* [ 0 ] response flow control frame enable in full-duplex mode. */
		unsigned int rx_fdfc : 1;
	} bits;

	/* Define an unsigned member */
	unsigned int    u32;
} pause_en_u;

/* Define the union short_framesize */
/* SHORT_RUNTS_THR is ultra-short frame threshold register. */
/* 0x50 */
union short_framesize {
	/* Define the struct bits */
	struct {
		/* [ 31..5 ] cannot be configured. */
		unsigned int reserved_14 : 27;
		/* [ 4..0 ] short frames, ultra-short frame boundaries for statistics. */
		unsigned int short_runts_thr : 5;
	} bits;

	/* Define an unsigned member */
	unsigned int    u32;
};

/* 0x58 */
union an_neg_state {
	/* Define the struct bits */
	struct {
		unsigned int reserved_1 : 10;
		unsigned int an_done : 1;
		unsigned int rx_sync_ok : 1;
		unsigned int reserved_2 : 4;
		unsigned int np_link_ok : 1;
		unsigned int reserved_3 : 1;
		unsigned int rf2 : 1;
		unsigned int rf1_duplex : 1;
		unsigned int speed : 2;
		unsigned int reserved_4 : 1;
		unsigned int ps : 2;
		unsigned int hd : 1;
		unsigned int fd : 1;
		unsigned int reserved_5 : 5;
	} bits;

	/* Define an unsigned member */
	unsigned int    u32;
};

/* Define the union normal_control */
/* TRANSMIT_CONTROL is common configuration register. */
/* 0x60 */
union normal_control {
	/* Define the struct bits */
	struct {
		/* [ 31..8 ] cannot be configured. */
		unsigned int reserved_16 : 24;
		/* [ 7 ] sends a PAD control. */
		unsigned int pad_enable : 1;
		/* [ 6 ] to send FCS control. */
		unsigned int crc_add : 1;
		/* [ 5 ] cannot be configured. */
		unsigned int an_enable : 1;
		/* [ 4..0 ] cannot be configured. */
		unsigned int reserved_18 : 5;
	} bits;

	/* Define an unsigned member */
	unsigned int    u32;
};

/* Define the union REC_FILT_CONTROL_U */
/* REC_FILT_CONTROL is Filter control register for the receive frame. */
/* 0x64 */
typedef union tagrecfiltcontrol {
	/* Define the struct bits */
	struct {
		/* [ 31..6 ] cannot be configured. */
		unsigned int reserved_20 : 26;
		/* Report control  [5] CRC error frames. */
		unsigned int crc_err_pass : 1;
		/* [ 4 ] flow control frame filtering enable bit (the response flow control
		 * frames rx_fdfc valid, this configuration item takes effect.
		 */
		unsigned int pause_frm_pass : 1;
		/* [ 3 ] cannot be configured. */
		unsigned int reserved_21 : 1;
		/* [ 2 ] broadcast frame filtering control. */
		unsigned int bc_drop_en : 1;
		/* [ 1 ] multicast frame filtering control. */
		unsigned int mc_match_en : 1;
		/* [0] DA not match unicast frame filtering. */
		unsigned int uc_match_en : 1;
	} bits;

	/* Define an unsigned member */
	unsigned int    u32;
} rec_filt_control_u;

/* Define the union LED_MOD_U */
/* LED_MOD is indicator mode control register. */
/* 0x16C */
typedef union tagledmod {
	/* Define the struct bits */
	struct {
		/* [ 31..1 ] cannot be configured. */
		unsigned int reserved_26 : 31;
		/* [0] Activity LED indicator mode. */
		unsigned int led_mod : 1;
	} bits;

	/* Define an unsigned member */
	unsigned int    u32;
} led_mod_u;

/* Define the union LINE_LOOP_BACK_U */
/* LINE_LOOP_BACK is MAC line-side loopback register. */
/* 0x1A8 */
typedef union taglineloopback {
	/* Define the struct bits */
	struct {
		/* [ 31..1 ] cannot be configured. */
		unsigned int reserved_28 : 31;
		/* [0] MAC line-side loopback enable. */
		unsigned int line_loop_back : 1;
	} bits;

	/* Define an unsigned member */
	unsigned int    u32;
} line_loop_back_u;

/* Define the union crc_strip */
/* CF_CRC_STRIP is CRC strip enable register. */
/* 0x1B0 */
union crc_strip {
	/* Define the struct bits */
	struct {
		/* [ 31..1 ] cannot be configured. */
		unsigned int reserved_30 : 31;
		/* [ 0 ] Receive CRC strip enable. */
		unsigned int cf_crc_strip : 1;
	} bits;

	/* Define an unsigned member */
	unsigned int    u32;
};

/* Define the union mode_change_en */
/* MODE_CHANGE_EN is the port mode change enable register. */
/* 0x1B4 */
union mode_change_en {
	/* Define the struct bits */
	struct {
		/* [ 31..1 ] cannot be configured. */
		unsigned int reserved_32 : 31;
		/* Port mode change enable [ 0 ]. */
		unsigned int mode_change_en : 1;
	} bits;

	/* Define an unsigned member */
	unsigned int    u32;
};

/* Define the union LOOP_REG_U */
/* Supplementary LOOP_REG is a loopback register. */
/* 0x1DC */
typedef union tagloopreg {
	/* Define the struct bits */
	struct {
		/* [ 31..3 ] cannot be configured. */
		unsigned int reserved_33 : 29;
		/* [ 2 ] application side loopback enable. */
		unsigned int cf2mi_lp_en : 1;
		/* [ 1 ] line-side loopback,MAC data read/write enable signal source select. */
		unsigned int cf_ext_drive_lp : 1;
		/* [ 0 ] cannot be configured. */
		unsigned int reserved_34 : 1;
	} bits;

	/* Define an unsigned member */
	unsigned int    u32;
} loop_reg_u;

/* Define the union recv_control */
/* RECV_CONTROL is an RX control register. */
/* 0x1E0 */
union recv_control {
	/* Define the struct bits */
	struct {
		/* [ 31..5 ] cannot be configured. */
		unsigned int reserved_36 : 27;
		/* Short frames received  [ 4 ] transparent transmission enable. */
		unsigned int runt_pkt_en : 1;
		/* [ 3 ] PAD strip control frames received. */
		unsigned int strip_pad_en : 1;
		/* [ 2..0 ] cannot be configured. */
		unsigned int reserved_37 : 3;
	} bits;

	/* Define an unsigned member */
	unsigned int    u32;
};

/* Define the union VLAN_CODE_U */
/* VLAN_CODE is VLAN Code register. */
/* 0x1E8 */
typedef union tagvlancode {
	/* Define the struct bits */
	struct {
		/* [ 31..16 ] cannot be configured. */
		unsigned int reserved_38 : 16;
		/* [15..0] Ethernet Type Domain Configuration (The PCU can only identify 0x8100 vlan,
		 * so please do not set to other values.
		 */
		unsigned int cf_vlan_code : 16;
	} bits;

	/* Define an unsigned member */
	unsigned int    u32;
} vlan_code_u;

/* Define the union STATION_ADDR_HIGH_0_U */
/* STATION_ADDR_HIGH is the local MAC address 2 0 register. */
/* 0x204 */
typedef union tagstationaddrhigh0 {
	/* Define the struct bits */
	struct {
		/* [ 31..17 ] cannot be configured. */
		unsigned int reserved_41 : 15;
		/* [ 16 ] enable this address. */
		unsigned int station_addr_0_en : 1;
		/* High 16bit [15..0] MAC source address. */
		unsigned int station_addr_high_0 : 16;
	} bits;

	/* Define an unsigned member */
	unsigned int    u32;
} station_addr_high_0_u;

/* Define the union STATION_ADDR_HIGH_1_U */
/* STATION_ADDR_HIGH is the local MAC address 2 1 register. */
/* 0x20C */
typedef union tagstationaddrhigh1 {
	/* Define the struct bits */
	struct {
		/* [ 31..17 ] cannot be configured. */
		unsigned int reserved_43 : 15;
		/* [ 16 ] enable this address. */
		unsigned int station_addr_1_en : 1;
		/* High 16bit [15..0] MAC source address. */
		unsigned int station_addr_high_1 : 16;
	} bits;

	/* Define an unsigned member */
	unsigned int    u32;
} station_addr_high_1_u;

/* Define the union STATION_ADDR_HIGH_2_U */
/* STATION_ADDR_HIGH is the local MAC address 2 2 register. */
/* 0x214 */
typedef union tagstationaddrhigh2 {
	/* Define the struct bits */
	struct {
		/* [ 31..17 ] cannot be configured. */
		unsigned int reserved_44 : 15;
		/* [ 16 ] enable this address. */
		unsigned int station_addr_2_en : 1;
		/* High 16bit [15..0] MAC source address. */
		unsigned int station_addr_high_2 : 16;
	} bits;

	/* Define an unsigned member */
	unsigned int    u32;
} station_addr_high_2_u;

/* Define the union STATION_ADDR_HIGH_3_U */
/* STATION_ADDR_HIGH is the local MAC address 2 3 register. */
/* 0x21C */
typedef union tagstationaddrhigh3 {
	/* Define the struct bits */
	struct {
		/* [ 31..17 ] cannot be configured. */
		unsigned int reserved_45 : 15;
		/* [ 16 ] enable this address. */
		unsigned int station_addr_3_en : 1;
		/* High 16bit [15..0] MAC source address. */
		unsigned int station_addr_high_3 : 16;
	} bits;

	/* Define an unsigned member */
	unsigned int    u32;
} station_addr_high_3_u;

/* Define the union STATION_ADDR_HIGH_4_U */
/* STATION_ADDR_HIGH is the local MAC address 2 4 register. */
/* 0x224 */
typedef union tagstationaddrhigh4 {
	/* Define the struct bits */
	struct {
		/* [ 31..17 ] cannot be configured. */
		unsigned int reserved_46 : 15;
		/* [ 16 ] enable this address. */
		unsigned int station_addr_4_en : 1;
		/* High 16bit [15..0] MAC source address. */
		unsigned int station_addr_high_4 : 16;
	} bits;

	/* Define an unsigned member */
	unsigned int    u32;
} station_addr_high_4_u;

/* Define the union STATION_ADDR_HIGH_5_U */
/* STATION_ADDR_HIGH is the local MAC address 2 5 register. */
/* 0x22C */
typedef union tagstationaddrhigh5 {
	/* Define the struct bits */
	struct {
		/* [ 31..17 ] cannot be configured. */
		unsigned int reserved_47 : 15;
		/* [ 16 ] enable this address. */
		unsigned int station_addr_5_en : 1;
		/* High 16bit [15..0] MAC source address. */
		unsigned int station_addr_high_5 : 16;
	} bits;

	/* Define an unsigned member */
	unsigned int    u32;
} station_addr_high_5_u;

/* Define the union STATION_ADDR_HIGH_MSK_0_U */
/* STATION_ADDR_HIGH is the local MAC address 0 2 mask register. */
/* 0x234 */
typedef union tagstationaddrhighmsk0 {
	/* Define the struct bits */
	struct {
		/* [ 31..16 ] cannot be configured. */
		unsigned int reserved_48 : 16;
		/* [ 15..0 ] is the local MAC address mask 2 high-16bit 0 register. */
		unsigned int station_addr_high_msk_0 : 16;
	} bits;

	/* Define an unsigned member */
	unsigned int    u32;
} station_addr_high_msk_0_u;

/* Define the union STATION_ADDR_HIGH_MSK_1_U */
/* STATION_ADDR_HIGH is the local MAC address 1 2 mask register. */
/* 0x23C */
typedef union tagstationaddrhighmsk1 {
	/* Define the struct bits */
	struct {
		/* [ 31..16 ] cannot be configured. */
		unsigned int reserved_49 : 16;
		/* [ 15..0 ] local MAC address 1 mask register 2 high-16bit. */
		unsigned int station_addr_high_msk_1 : 16;
	} bits;

	/* Define an unsigned member */
	unsigned int    u32;
} station_addr_high_msk_1_u;

/* Define the union MAC_SKIP_LEN_U */
/* SKIP_LEN is header does not parse the field length. */
/* 0x240 */
typedef union tagmacskiplen {
	/* Define the struct bits */
	struct {
		/* [ 31..7 ] are reserved. */
		unsigned int reserved_50 : 25;
		/* [6] CRC calculation contain skip area. */
		unsigned int mac_skip_crc : 1;
		/* [ 5..0 ] to packet header does not parse the field length.
		 * The unit is byte (the value is 48 bytes).
		 */
		unsigned int mac_skip_len : 6;
	} bits;

	/* Define an unsigned member */
	unsigned int    u32;
} mac_skip_len_u;

/* Define the union DMAC_WITH_MSK_EN_U */
/* DMAC to share 32 with local MAC address mask enable. . */
/* 0x374 */
typedef union tagdmacwithmsken {
	/* Define the struct bits */
	struct {
		/* [ 31..6 ] are reserved. */
		unsigned int reserved_52 : 26;
		/* [ 5..0 ] 5-0 correspond to Article 5-0 with local MAC address mask enable. */
		unsigned int dmac_with_msk_en : 6;
	} bits;

	/* Define an unsigned member */
	unsigned int    u32;
} dmac_with_msk_en_u;

/* Define the union TX_LOOP_PKT_PRI_U */
/* Specifies the loopback packet priority-level configuration. */
/* 0x378 */
typedef union tagtxlooppktpri {
	/* Define the struct bits */
	struct {
		/* [ 31..2 ] are reserved. */
		unsigned int reserved_53 : 30;
		/* [ 1 ] The packet loopback enable. */
		unsigned int loop_pkt_en : 1;
		/* [ 0 ] specified packet priority level. The value 1 indicates
		 * that loopback packets and discard received packets when receiving packets conflict.
		 */
		unsigned int loop_pkt_hig_pri : 1;
	} bits;

	/* Define an unsigned member */
	unsigned int    u32;
	} tx_loop_pkt_pri_u;

#endif /* GMAC_GE_REG_H */
